ARM GIC-400 寄存器【转】
转自：
1.简介
GIC-400是用于控制中断的。在cubieboard2 上 的A20芯片采用了这款控制器。
cubieboard2 的GIC控制器 的地址是0x01C80000---0x01C87FFF ，长度等于GIC-400寄存器的长度。
具体的内容如下所示。
以0x01C80000为起始地址，下面给出的是偏移：
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Reserved 未使用，无用 |
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Distributor 配置器 有用 |
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CPU interfaces CPU接口 有用 |
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Virtual interface control block, for the processor that is performing the access 虚拟化相关，无用 |
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Virtual interface control block, for the processor selected by address bits [11:9] 虚拟化相关，无用 |
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Alias for Processor 0 Alias for Processor 1 ... Alias for Processor 7 |
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Virtual CPU interfaces 虚拟化相关，无用 |
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常用的是图中第二块和第三块，0x1000~0x3fff这部分的配置。
2.Distributor 配置器
distributor这块寄存器的地址 = GIC控制器 的地址 + 0x1000 ，使用的时候别忘记了偏移。然后从这里开始，有如下的寄存器
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偏移 |
名称 |
可读写 |
复位后 |
作用 |
|---|---|---|---|---|
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GICD_CTLR |
RW |
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Distributor Control Register 写入1使能控制器，必备 |
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GICD_TYPER |
RO |
Configuration-dependent[d] |
Interrupt Controller Type Register 其中可以查看中断线的总数 |
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GICD_IIDR |
RO |
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Distributor Implementer Identification Register, GICD_IIDR 存了一些版本信息，没用 |
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GICD_IGROUPRn |
RW |
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Interrupt Group Registers[e] 一个位图，控制中断属于A组还是B组 |
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GICD_ISENABLERn |
RW[f] |
SGIs and PPIs: |
Interrupt Set-Enable Registers 一个位图，用于使能各个中断，写入1使能。有用 |
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SPIs: |
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GICD_ICENABLERn |
RW[f] |
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Interrupt Clear-Enable Registers 和上一个寄存器类似，作用相反，写入1禁止。 |
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GICD_ISPENDRn |
RW |
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Interrupt Set-Pending Registers pend位图，写入1可以进入pend状态 |
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GICD_ICPENDRn |
RW |
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Interrupt Clear-Pending Registers 同上，写入1效果相反，阻止pend状态 |
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GICD_ISACTIVERn |
RW |
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Interrupt Set-Active Registers 位图，写入1可以激活中断 |
0x380-0x3BC |
GICD_ICACTIVERn |
RW |
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Interrupt Clear-Active Registers 写入1反激活中断 |
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GICD_IPRIORITYRn |
RW |
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Interrupt Priority Registers 存着各个中断的优先级，每8位算一个 |
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GICD_ITARGETSRn |
RO[h] |
Interrupt Processor Targets Registers[i] 某个中断应该发往哪个处理器进行处理 |
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RW |
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GICD_ICFGRn |
RO |
SGIs: |
Interrupt Configuration Registers, GICD_ICFGRn 配置中断是低电平触发还是下降沿触发 |
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RO |
PPIs: |
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RW[j] |
SPIs: |
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0xD00 |
GICD_PPISR |
RO |
0x00000000 |
Private Peripheral Interrupt Status Register, GICD_PPISR 一般没用 |
0xD04-0xD3C |
GICD_SPISRn |
RO |
0x00000000 |
Shared Peripheral Interrupt Status Registers, GICD_SPISRn 没用 |
0xF00 |
GICD_SGIR |
WO |
- |
Software Generated Interrupt Register 控制软中断 |
0xF10-0xF1C |
GICD_CPENDSGIRn |
RW |
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SGI Clear-Pending Registers 软中断的pend位 |
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GICD_SPENDSGIRn |
RW |
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SGI Set-Pending Registers 同上，不过写入1时停止pend |
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GICD_PIDR4 |
RO |
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Peripheral ID 4 Register |
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GICD_PIDR5 |
RO |
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Peripheral ID 5 Register |
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GICD_PIDR6 |
RO |
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Peripheral ID 6 Register |
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GICD_PIDR7 |
RO |
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Peripheral ID 7 Register |
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GICD_PIDR0 |
RO |
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Peripheral ID 0 Register |
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GICD_PIDR1 |
RO |
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Peripheral ID 1 Register |
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GICD_PIDR2 |
RO |
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Peripheral ID 2 Register |
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GICD_PIDR3 |
RO |
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Peripheral ID 3 Register |
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GICD_CIDR0 |
RO |
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Component ID 0 Register |
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GICD_CIDR1 |
RO |
0x000000F0 |
Component ID 1 Register |
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GICD_CIDR2 |
RO |
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Component ID 2 Register |
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GICD_CIDR3 |
RO |
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Component ID 3 Register |
3.cpu接口
开始地址的偏移量为0x2000
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Offset |
Name |
Type |
Reset |
Description[a] |
|---|---|---|---|---|
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GICC_CTLR |
RW |
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CPU Interface Control Register 使能位。写入1使能 |
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GICC_PMR |
RW |
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Interrupt Priority Mask Register 限制中断最低优先级，高于此值无法中断，最好写大一点 |
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GICC_BPR |
RW |
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Binary Point Register The minimum value of the Binary Point Register depends on which security-banked copy is considered:
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GICC_IAR |
RO |
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Interrupt Acknowledge Register 只读，中断id |
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GICC_EOIR |
WO |
- |
End of Interrupt Register 写入以告知cpu已经处理完中断 |
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GICC_RPR |
RO |
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Running Priority Register 当前中断优先级 |
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GICC_HPPIR |
RO |
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Highest Priority Pending Interrupt Register [c] 最高优先级中断号及其pend值 |
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GICC_ABPR |
RW |
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Aliased Binary Point Register[d] The minimum value of the Aliased Binary Point Register is 别名寄存器 |
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GICC_AIAR |
RO |
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Aliased Interrupt Acknowledge Register[d] 别名寄存器 |
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GICC_AEOIR |
WO |
Aliased End of Interrupt Register[d] 别名寄存器 |
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GICC_AHPPIR |
RO |
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Aliased Highest Priority Pending Interrupt Register[c][d] 别名寄存器 |
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GICC_APR0 |
RW |
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Active Priority Register 用于保存和恢复 |
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GICC_NSAPR0 |
RW |
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Non-Secure Active Priority Register[d] 用于保存和恢复 |
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GICC_IIDR |
RO |
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CPU Interface Identification Register, GICC_IIDR 存着版本信息 |
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GICC_DIR |
WO |
- |
Deactivate Interrupt Register |